C8051F52X_12 Datasheet, PDF (150/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x99
Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB–LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When
data is written to SBUF0, it goes to the transmit shift register and is held for serial transmis-
sion. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the con-
tents of the receive latch.
Table 15.1. Timer Settings for Standard Baud Rates 
Using the Internal Oscillator
Frequency: 24.5 MHz
Target
Baud Rate
(bps)
230400
115200
57600
28800
14400
9600
2400
1200
Baud Rate
% Error
Timer Clock
Oscillator Source
Divide
Factor
SCA1–SCA0
(pre-scale
select)*
T1M* Timer 1
Reload
Value (hex)
–0.32%
106
SYSCLK
XX
–0.32%
212
SYSCLK
XX
0.15%
426
SYSCLK
XX
–0.32%
848 SYSCLK / 4
01
0.15%
1704 SYSCLK / 12
00
1
0xCB
1
0x96
1
0x2B
0
0x96
0
0xB9
–0.32%
2544 SYSCLK / 12
00
0
0x96
–0.32%
10176 SYSCLK / 48
10
0
0x96
0.15%
20448 SYSCLK / 48
10
0
0x2B
X = Don’t care
Note: SCA1–SCA0 and T1M bit definitions can be found in Section 18.1.
150
Rev. 1.4