C8051F52X_12 Datasheet, PDF (115/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
12.2. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of V_DD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
12.2.1. V_DD Maintenance and the V_DD monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the maximum V_DD ramp time specification (if applicable) is met. See Section 20.4 on
page 211 for more details on V_DD ramp time. If the system cannot meet this ramp time specification,
then add an external V_DD brownout circuit to the RST pin of the device that holds the device in reset
until V_DD reaches the minimum specified V_DD and re-asserts RST if V_DD drops belowthat level.
V_DD (min) is specified in Table 2.2 on page 26.
3. Enable the on-chip V_DD monitor (VDDMON0) and enable it as a reset source as early in code as
possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
V_DD monitor (VDDMON0) and enabling it as a reset source. Code examples showing this can be found
in “AN201: Writing to Flash from Firmware", available from the Silicon Laboratories web site.
4. As an added precaution, explicitly enable the V_DD monitor (VDDMON0) and enable the V_DD monitor as
a reset source inside the functions that write and erase Flash memory. The V_DD monitor enable
instructions should be placed just after the instruction to set PSWE to a 1, but before the Flash write or
erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
12.2.2. PSWE Maintenance
1. Reduce the number of places in code where the PSWE bit (PSCTL.0) is set to a 1. There should be
exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets
PSWE and PSEE both to a 1 to erase Flash pages.
2. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing
this can be found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories
web site.
3. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
4. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
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