C8051F52X_12 Datasheet, PDF (213/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
20.8. UART Pins
The location of the pins used by the serial UART interface differs between the silicon revisions of
C8051F52x/52xA/F53x/F53xA devices.
On Revision A devices, the TX and RX pins used by the UART interface are mapped to the P0.3 (TX) and
P0.4 (RX) pins. Beginning with Revision B devices, the TX and RX pins used by the UART interface are
mapped to the P0.4 (TX) and P0.5 (RX) pins.
Important Note: On Revision B and newer devices, the UART pins must be skipped if the UART is
enabled in order for peripherals to appear on port pins beyond the UART on the crossbar. For example,
with the SPI and UART enabled on the crossbar with the SPI on P1.0-P1.3, the UART pins must be
skipped using P0SKIP for the SPI pins to appear correctly.
20.9. LIN
The LIN peripheral behavior differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA devices.
The differences are:
20.9.1. Stop Bit Check
On Revision A devices, the stop bits of the fields in the LIN frame are not checked and no error is gener-
ated if the stop bits could not be sent or received correctly. On Revision B and Revision C devices, the stop
bits are checked, and an error will be generated if the stop bit was not sent or received correctly.
20.9.2. Synch Break and Synch Field Length Check
On Revision A devices, the check of sync field length versus sync break length is incorrect. On Revision B
and Revision C devices, the sync break length must be larger than 10 bit times (of the measured bit time)
to enable the synchronization.
Rev. 1.4
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