C8051F52X_12 Datasheet, PDF(109/221 Page) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

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C8051F52X_12 Datasheet, PDF (109/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

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C8051F52x/F53x

ramp or during a brownout condition even when VDD is below the specified minimum of 2.0 V. There are

two possible ways to handle this transitional period as described below:

If using the on-chip regulator (REG0) at the 2.6 V setting (default), it is recommended that user software

set the VDDMON0 threshold to its high setting (VRST-HIGH) as soon as possible after reset by setting the

VDMLVL bit to 1 in SFR Definition 11.1 (VDDMON). In this typical configuration, no external hardware or

additional software routines are necessary to monitor the VDD level.

Note: Please refer to Section â20.5. VDD Monitor (VDDMON0) High Threshold Settingâ on page 212 for important

notes related to the VDD Monitor high threshold setting in older silicon revisions A and B.ï

If using the on-chip regulator (REG0) at the 2.1 V setting or if directly driving VDD with REG0 disabled, the

user system (software/hardware) should monitor VDD at power-on and also during device operation. The

two key parameters that can be affected when VDD < 2.0 V are: internal oscillator frequency (Table 2.11 on

page 34) and minimum ADC tracking time (Table 2.3 on page 28).

SFR Definition 11.1. VDDMON: VDD Monitor Control

R/W

VDMEN

Bit7

R

R/W

VDDSTAT VDMLVL

Bit6

Bit5

R

R

R

R

R

Reset Value

VDM1EN Reserved Reserved Reserved Reserved 1v010000

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xFF

Bit7: VDMEN: VDD Monitor Enable (VDDMON0).

This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate system

resets until it is also selected as a reset source in register RSTSRC (SFR Definition 11.2).

The VDD Monitor can be allowed to stabilize before it is selected as a reset source. Select-

ing the VDD monitor as a reset source before it has stabilized may generate a system

reset. See Table 2.8 on page 32 for the minimum VDD Monitor turn-on time.

0: VDD Monitor Disabled.ï

1: VDD Monitor Enabled (default).

Bit6: VDDSTAT: VDD Status.

This bit indicates the current power supply status (VDD Monitor output).

0: VDD is at or below the VDD Monitor (VDDMON0) Threshold.

1: VDD is above the VDD Monitor (VDDMON0) Threshold.

Bit5: VDMLVL: VDD Level Select.

0: VDD Monitor (VDDMON0) Threshold is set to VRST-LOW (default).

1: VDD Monitor (VDDMON0) Threshold is set to VRST-HIGH. This setting is required for any

system that includes code that writes to and/or erases Flash.

Bit4:

VDM1EN*: Level-sensitive VDD Monitor Enable (VDDMON1).

This bit turns the VDD monitor circuit on/off. If turned on, it is also selected as a reset

source, and can generate a system reset.

0: Level-sensitive VDD Monitor Disabled.

1: Level-sensitive VDD Monitor Enabled (default).

Bits3â0: RESERVED. Read = Variable. Write = donât care.

*Note: Available only on the C8051F52x-C/F53x-C devices

Rev. 1.4

109

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