C8051F52X_12 Datasheet, PDF (22/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
1.5. 12-Bit Analog to Digital Converter
The C8051F52x/F52xA/F53x/F53xA devices include an on-chip 12-bit SAR ADC with a maximum through-
put of 200 ksps. The ADC system includes a configurable analog multiplexer that selects the positive ADC
input, which is measured with respect to GND. Ports 0 and 1 are available as ADC inputs; additionally, the
ADC includes an innovative programmable gain stage which allows the ADC to sample inputs sources
greater than the VREF voltage. The on-chip Temperature Sensor output and the core supply voltage (V_DD)
are also available as ADC inputs. User firmware may shut down the ADC or use it in Burst Mode to save
power.
Conversions can be initiated in four ways: a software command, an overflow of Timer 1, an overflow of
Timer 2, or an external convert start signal. This flexibility allows the start of conversion to be triggered by
software events, a periodic signal (timer overflows), or external HW signals. Conversion completions are
indicated by a status bit and an interrupt (if enabled) and occur after 1, 4, 8, or 16 samples have been
accumulated by a hardware accumulator. The resulting 12-bit to 16-bit data word is latched into the ADC
data SFRs upon completion of a conversion. When the system clock is slow, Burst Mode allows ADC0 to
automatically wake from a low power shutdown state, acquire and accumulate samples, then re-enter the
low power shutdown state without CPU intervention.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
P0.0
P0.6*
P0.7*
P1.0*
Configuration, Control, and Data Registers
Burst Mode
Logic
Start
Conversion
AD0BUSY (W)
Timer 1 Overflow
CNVSTR Rising Edge
Timer 2 Overflow
P1.7*
* Available on ‘F53x/
’F53xA devices
19-to-1
AMUX
Selectable
Gain
Temp
Sensor
VDD
GND
12-Bit
SAR
ADC
End of
Conversion
Interrupt
ADC Data
16
Registers
Accumulator
Window Compare
Logic
Window
Compare
Interrupt
Figure 1.7. 12-Bit ADC Block Diagram
22
Rev. 1.4