C8051F52X_12 Datasheet, PDF (183/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 18.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 10.5. IT01CF: INT0/INT1
Configuration). Setting GATE0 to 1 allows the timer to be controlled by the external input signal INT0 (see
Section “10.4. Interrupt Register Descriptions” on page 100), facilitating pulse width measurements.
TR0
GATE0
0
X
1
0
1
1
1
1
X = Don't Care
INT0
X
X
0
1
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT0 is used with Timer 1; the INT0 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 10.5. IT01CF: INT0/INT1 Configuration).
IT01CF
Figure 18.1. T0 Mode 0 Block Diagram
Rev. 1.4
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