C8051F52X_12 Datasheet, PDF (52/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
4. 12-Bit ADC (ADC0)
The ADC0 on the C8051F52x/F52xA/F53x/F53xA Family consists of an analog multiplexer (AMUX0) with
16/6 total input selections, and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with inte-
grated track-and-hold, programmable window detector, programmable gain, and hardware accumulator.
The ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and accu-
mulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0,
data conversion modes, and window detector are all configurable under software control via the Special
Function Registers shown in Figure 4.1. ADC0 inputs are single-ended and may be configured to measure
P0.0-P1.7, the Temperature Sensor output, V_DD, or GND with respect to GND. The voltage reference for
the ADC is selected as described in Section “5. Voltage Reference” on page 72. ADC0 is enabled when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
ADC0MX
ADC0TK
ADC0CN
P0.0
P0.6*
P0.7*
P1.0*
P1.7*
*Available on ‘F53x/’F53xA
devices
VDD
Temp Sensor
GND
19-to-1
AMUX0
Start
Conversion
SYSCLK
Burst Mode
Logic
Burst Mode
Oscillator
25 MHz Max
Selectable
Gain
VDD
12-Bit
SAR
ADC
00
Start
01
Conversion
10
11
AD0BUSY (W)
Timer 1 Overflow
CNVSTR Input
Timer 2 Overflow
Accumulator
ADC0GNH ADC0GNL ADC0GNA
AD0WINT
ADC0LTH ADC0LTL
Window
Compare
32 Logic
ADC0CF
ADC0GTH ADC0GTL
Figure 4.1. ADC0 Functional Block Diagram
4.1. Analog Multiplexer
AMUX0 selects the input channel to the ADC. Any of the following may be selected as an input: P0.0–
P1.7, the on-chip temperature sensor, the core power supply (V_DD), or ground (GND). ADC0 is single-
ended and all signals measured are with respect to GND. The ADC0 input channels are selected using
the ADC0MX register as described in SFR Definition 4.4.
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN (for n = 0,1). To force the Crossbar to skip a Port
pin, set to 1 the corresponding bit in register PnSKIP (for n = 0,1). See Section “13. Port Input/Output” on
page 120 for more Port I/O configuration details.
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Rev. 1.4