C8051F52X_12 Datasheet, PDF (92/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
9. Memory Organization and SFRs
The memory organization of the C8051F52x/F52xA/F53x/F53xA is similar to that of a standard 8051.
There are two separate memory spaces: program memory and data memory. Program and data memory
share the same address space but are accessed via different instruction types. The memory map is shown
in Figure 9.1.
PROGRAM/DATA MEMORY
(Flash)
'F520/0A/1/1A and 'F530/0A/1/1A
0x1E00
0x1DFF
RESERVED
8 kB Flash
0x0000
(In-System
Programmable in 512
Byte Sectors)
'F523/3A/4/4A and 'F533/3A/4/4A
0x1000
0x0FFF
RESERVED
4 kB Flash
0x0000
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
'F526/6A/7/7A and 'F536/6A/7/7A
0x0800
0x07FF
RESERVED
2 kB Flash
0x0000
(In-System
Programmable in 512
Byte Sectors)
Figure 9.1. Memory Map
9.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F520/0A/1/1A and C8051F530/0A/1/1A
implement 8 kB of this program memory space as in-system, re-programmable Flash memory, organized
in a contiguous block from addresses 0x0000 to 0x1FFF. Addresses above 0x1DFF are reserved on the
8 kB devices. The C8051F523/3A/4/4A and C8051F533/3A/4/4A implement 4 kB of Flash from addresses
0x0000 to 0x0FFF. The C8051F526/6A/7/7A and C8051F536/6A/7/7A implement 2 kB of Flash from
addresses 0x0000 to 0x07FF.
Program memory is normally assumed to be read-only. However, the C8051F52x/F52xA/F53x/F53xA can
write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX
write instruction. This feature provides a mechanism for updates to program code and use of the program
memory space for non-volatile data storage. Refer to Section “12. Flash Memory” on page 113 for further
details.
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Rev. 1.4