C8051F52X_12 Datasheet, PDF (95/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
Table 9.2. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
ACC
ADC0CF
ADC0CN
ADC0H
ADC0L
ADC0GTH
ADC0GTL
ADC0LTH
ADC0LTL
ADC0MX
ADC0TK
B
Address
0xE0
0xBC
0xE8
0xBE
0xBD
0xC4
0xC3
0xC6
0xC5
0xBB
0xBA
0xF0
Description
Accumulator
ADC0 Configuration
ADC0 Control
ADC0
ADC0
ADC0 Greater-Than Data High Byte
ADC0 Greater-Than Data Low Byte
ADC0 Less-Than Data High Byte
ADC0 Less-Than Data Low Byte
ADC0 Channel Select
ADC0 Tracking Mode Select
B Register
CKCON
CLKSEL
CPT0CN
CPT0MD
CPT0MX
DPH
DPL
0x8E
0xA9
0x9B
0x9D
0x9F
0x83
0x82
Clock Control
Clock Select
Comparator0 Control
Comparator0 Mode Selection
Comparator0 MUX Selection
Data Pointer High
Data Pointer Low
EIE1
EIP1
FLKEY
IE
IP
IT01CF
LINADDR
LINCF
0xE6
0xF6
0xB7
0xA8
0xB8
0xE4
0x92
0x95
Extended Interrupt Enable 1
Extended Interrupt Priority 1
Flash Lock and Key
Interrupt Enable
Interrupt Priority
INT0/INT1 Configuration
LIN indirect address pointer
LIN master-slave and automatic baud rate selection
LINDATA
OSCICL
0x93
0xB3
LIN indirect data buffer
Internal Oscillator Calibration
Page
89
65
67
66
66
69
69
70
70
64
68
89
188
143
78
80
79
87
87
102
103
119
100
101
105
172
173
172
138
Rev. 1.4
95