C8051F52X_12 Datasheet, PDF (32/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
Table 2.8. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min
Typ Max Units
RST Output Low Voltage
I_OL = 8.5 mA, V_DD =
2.1 V
—
—
0.8
V
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Impedance
Missing Clock Detector Timeout
Reset Time Delay (T_PORDelay)¹
0.7 x
V_REGIN
—
V_REGIN = 1.8 V
—
V_REGIN = 2.7 V
—
V_REGIN = 3.3 V
—
V_REGIN = 5 V
—
Time from last system
clock rising edge to reset 100
initiation
Delay between release
of any reset source and
code execution at loca-
—
tion 0x0000
—
—
V
—
0.3 x
V_REGIN
V
330
—
k
160
—
k
130
—
k
80
—
k
350
650
µs
—
350 µs
Minimum RST Low Time to Generate a
System Reset
10
—
—
µs
V_DD Monitor (VDDMON0)
Low Threshold (V_RST-LOW)^1,2,3
High Threshold (V_RST-HIGH)³
C8051F52x/53x
C8051F52xA/53xA
C8051F52x-C/53x-C
C8051F52x/53x
C8051F52xA/53xA
C8051F52x-C/53x-C
1.8
1.9
2.0
V
1.65
1.75
1.8
V
1.65
1.75
1.8
V
2.1
2.2
2.3
V
2.25
2.3
2.4
V
2.25
2.3
2.45
V
Turn-on Time
—
83
—
µs
Supply Current
V_DD = 2.1 V
Level-Sensitive V_DD Monitor (VDDMON1)¹
Threshold (V_RST1)^1,2,3
C8051F52x-C/53x-C
Supply Current
C8051F52x-C/53x-C
—
1
2
µA
1.6
1.75
1.9
V
—
3
6
µA
Notes:
1. Refer to Section “20. Device Specific Behavior” on page 210.
2. The POR threshold (V_RST) is V_RST-LOW or V_RST1, whichever is higher.
3. The V_RSTthreshold for power fail / brownout is the higher of VDDMON0 and VDDMON1 thresholds, if both are
enabled.
32
Rev. 1.4