C8051F52X_12 Datasheet, PDF (179/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFR Definition 17.14. LIN0ERR: LIN0 ERROR Register
R
R
R
R
R
R
R
R
Reset Value
SYNCH PRTY TOUT
CHK
BITERR ^00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address: 0x0A (indirect)
Bits7–5: UNUSED. Read = 000b. Write = don’t care.
Bit4: SYNCH: Synchronization Error Bit (slave mode only).
0: No error with the SYNCH FIELD has been detected.
1: Edges of the SYNCH FIELD are outside of the maximum tolerance.
Bit3: PRTY: Parity Error Bit (slave mode only).
0: No parity error has been detected.
1: A parity error has been detected.
Bit2: TOUT: Timeout Error Bit.
0: A timeout error has not been detected.
1: A timeout error has been detected. This error is detected whenever one of the following
conditions is met:
•The master is expecting data from a slave and the slave does not respond.
•The slave is expecting data but no data is transmitted on the bus.
•A frame is not finished within the maximum frame length.
•The application does not set the DTACK bit (LIN0CTRL.4) or STOP bit (LIN0CTRL.7) until the
end of the reception of the first byte after the identifier.
Bit1: CHK: Checksum Error Bit.
0: Checksum error has not been detected.
1: Checksum error has been detected.
Bit0: BITERR: Bit Transmission Error Bit.
0: No error in transmission has been detected.
1: The bit value monitored during transmission is different than the bit value sent.
Rev. 1.4
179