C8051F52X_12 Datasheet, PDF (186/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFR Definition 18.1. TCON: Timer Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0x88
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to 1 when INT0 is active as
defined by bit IN1PL in register IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Con-
figuration” on page 105).
IT1: Interrupt 1 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is
configured active low or high by the IN1PL bit in the IT01CF register (see SFR
Definition 10.5. “IT01CF: INT0/INT1 Configuration” on page 105).
0: INT0 is level triggered.
1: INT0 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to 1 when INT0 is active as
defined by bit IN0PL in register IT01CF (see SFR Definition 10.5. “IT01CF: INT0/INT1 Con-
figuration” on page 105).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured INT0 interrupt will be edge or level sensitive. INT0 is
configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition 10.5.
“IT01CF: INT0/INT1 Configuration” on page 105).
0: INT0 is level triggered.
1: INT0 is edge triggered.
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Rev. 1.4