C8051F52X_12 Datasheet, PDF (63/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
Gain Register Definition 4.1. ADC0GNH: ADC0 Selectable Gain High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
GAINH[7:0]
11111100
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x04
Bits7–0: High byte of Selectable Gain Word.
Gain Register Definition 4.2. ADC0GNL: ADC0 Selectable Gain Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
GAINL[3:0]
Reserved Reserved Reserved Reserved 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x07
Bits7–4: Lower 4 bits of the Selectable Gain Word.
Bits3–0: Reserved. Must Write 0000b.
Gain Register Definition 4.3. ADC0GNA: ADC0 Additional Selectable Gain
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved Reserved Reserved Reserved Reserved Reserved GAINADD 00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x08
Bits7–1: Reserved. Must Write 0000000b.
Bit0: GAINADD: Additional Gain Bit.
Setting this bit adds 1/64 (0.016) gain to the gain value in the ADC0GNH and ADC0GNL
registers.
Rev. 1.4
63