C8051F52X_12 Datasheet, PDF (108/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
11.2. Power-Fail Reset / V_DD Monitors (VDDMON0 and VDDMON1)
C8051F52x-C/F53x-C devices include two V_DD monitors: a standard V_DD monitor (VDDMON0) and a
level-sensitive V_DD monitor (VDDMON1). VDDMON0 is primarily intended for setting a higher threshold to
allow safe erase or write of Flash memory from firmware. VDDMON1 is used to hold the device in a reset
state during power-up and brownout conditions.
Note: VDDMON1 is not present in older silicon revisions A and B. Please refer to Section “20.4. VDD Monitors and
VDD Ramp Time” on page 211 for more details.
When a power-down transition or power irregularity causes V_DD to drop below V_RST, the power supply
monitors (VDDMON0 and VDDMON1) will drive the RST pin low and hold the CIP-51 in a reset state (see
Figure 11.2). When V_DD returns to a level above V_RST, the CIP-51 will be released from the reset state.
Note that even though internal data memory contents are not altered by the power-fail reset, it is impossi-
ble to determine if V_DD dropped below the level required for data retention. If the PORSF flag reads 1, the
data may no longer be valid.
VDDMON0 is enabled and is selected as a reset source after power-on resets; however its defined state
(enabled/disabled) is not altered by any other reset source. For example, if VDDMON0 is disabled by soft-
ware, and a software reset is performed, VDDMON0 will still be disabled after that reset.
VDDMON1 is enabled and is selected as a reset source after power-on reset and any other type of reset.
There is no register setting that can disable this level-sensitive VDD monitor as a reset source.
To protect the integrity of Flash contents, the V_DD monitor (VDDMON0) must be enabled to the
higher setting (VDMLVL = '1') and selected as a reset source if software contains routines which
erase or write Flash memory. If the V_DD monitor is not enabled and set to the higher setting, any
erase or write performed on Flash memory will cause a Flash Error device reset.
Note: Please refer to Section “20.5. VDD Monitor (VDDMON0) High Threshold Setting” on page 212 for important
notes related to the VDD Monitor high threshold setting in older silicon revisions A and B.
The V_DD monitor (VDDMON0) must be enabled before it is selected as a reset source. Selecting the
VDDMON0 as a reset source before it is enabled and stabilized may cause a system reset. The procedure
for re-enabling the V_DD monitor and configuring the V_DD monitor as a reset source is shown below:
1. Enable the V_DD monitor (VDMEN bit in VDDMON = 1).
2. Wait for the V_DD monitor to stabilize (see Table 2.8 on page 32 for the V_DD Monitor turn-on time). Note:
This delay should be omitted if software contains routines which write or erase Flash memory.
3. Select the V_DD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 11.2 for V_DD monitor timing; note that the reset delay is not incurred after a V_DD monitor reset.
See Table 2.8 on page 32 for complete electrical characteristics of the V_DD monitor.
Note: Software should take care not to inadvertently disable the V_DD Monitor (VDDMON0) as a reset
source when writing to RSTSRC to enable other reset sources or to trigger a software reset. All
writes to RSTSRC should explicitly set PORSF to '1' to keep the V_DD Monitor enabled as a reset
source.
11.2.1. VDD Monitor Thresholds and Minimum VDD
The minimum operating digital supply voltage (V_DD) is specified as 2.0 V in Table 2.2 on page 26. The volt-
age at which the MCU is released from reset (V_RST) can be as low as 1.65 V based on the V_DD Monitor
thresholds that are specified in Table 2.8 on page 32. This could allow code execution during the power-up
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Rev. 1.4