C8051F52X_12 Datasheet, PDF (8/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
Figure 13.5. Crossbar Priority Decoder with No Pins Skipped (DFN 10) .............. 124
Figure 13.6. Crossbar Priority Decoder with Some Pins Skipped (DFN 10) ......... 125
Figure 14.1. Oscillator Diagram ............................................................................. 135
Figure 14.2. 32 kHz External Crystal Example ...................................................... 140
Figure 15.1. UART0 Block Diagram ...................................................................... 144
Figure 15.2. UART0 Baud Rate Logic ................................................................... 145
Figure 15.3. UART Interconnect Diagram ............................................................. 146
Figure 15.4. 8-Bit UART Timing Diagram .............................................................. 146
Figure 15.5. 9-Bit UART Timing Diagram .............................................................. 147
Figure 15.6. UART Multi-Processor Mode Interconnect Diagram ......................... 148
Figure 16.1. SPI Block Diagram ............................................................................ 151
Figure 16.2. Multiple-Master Mode Connection Diagram ...................................... 154
Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram ............ 154
Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram ............ 154
Figure 16.5. Data/Clock Timing Relationship ........................................................ 156
Figure 16.6. SPI Master Timing (CKPHA = 0) ....................................................... 161
Figure 16.7. SPI Master Timing (CKPHA = 1) ....................................................... 161
Figure 16.8. SPI Slave Timing (CKPHA = 0) ......................................................... 162
Figure 16.9. SPI Slave Timing (CKPHA = 1) ......................................................... 162
Figure 17.1. LIN Block Diagram ............................................................................ 164
Figure 18.1. T0 Mode 0 Block Diagram ................................................................. 183
Figure 18.2. T0 Mode 2 Block Diagram ................................................................. 184
Figure 18.3. T0 Mode 3 Block Diagram ................................................................. 185
Figure 18.4. Timer 2 16-Bit Mode Block Diagram ................................................. 190
Figure 18.5. Timer 2 8-Bit Mode Block Diagram ................................................... 191
Figure 18.6. Timer 2 Capture Mode Block Diagram .............................................. 192
Figure 19.1. PCA Block Diagram ........................................................................... 195
Figure 19.2. PCA Counter/Timer Block Diagram ................................................... 196
Figure 19.3. PCA Interrupt Block Diagram ............................................................ 197
Figure 19.4. PCA Capture Mode Diagram ............................................................. 198
Figure 19.5. PCA Software Timer Mode Diagram ................................................. 199
Figure 19.6. PCA High-Speed Output Mode Diagram ........................................... 200
Figure 19.7. PCA Frequency Output Mode ........................................................... 201
Figure 19.8. PCA 8-Bit PWM Mode Diagram ........................................................ 202
Figure 19.9. PCA 16-Bit PWM Mode ..................................................................... 203
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled ................................ 204
Figure 20.1. Device Package—TSSOP 20 ............................................................ 210
Figure 20.2. Device Package—QFN 20 ................................................................ 210
Figure 20.3. Device Package—DFN 10 ................................................................ 211
Figure 21.1. Typical C2 Pin Sharing ...................................................................... 216
8
Rev. 1.4