C8051F52X_12 Datasheet, PDF (80/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
R/W
R/W
R/W
R/W
R/W
Reserved —
CP0RIE CP0FIE
—
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
R/W
Reset Value
— CP0MD1 CP0MD0 00000010
Bit2
Bit1
Bit0 SFR Address:
0x9D
Bit7: RESERVED. Read = 0b. Must write 0b.
Bit6: UNUSED. Read = 0b. Write = don’t care.
Bit5: CP0RIE: Comparator Rising-Edge Interrupt Enable.
0: Comparator rising-edge interrupt disabled.
1: Comparator rising-edge interrupt enabled.
Bit4: CP0FIE: Comparator Falling-Edge Interrupt Enable.
0: Comparator falling-edge interrupt disabled.
1: Comparator falling-edge interrupt enabled.
Note: It is necessary to enable both CP0xIE and the correspondent ECPx bit located in EIE1
SFR.
Bits3–2: UNUSED. Read = 00b. Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select
These bits select the response time for Comparator0.
Mode CP0MD1 CP0MD0
0
0
0
1
0
1
2
1
0
3
1
1
CP0 Falling Edge Response
Time (TYP)
Fastest Response Time
—
—
Lowest Power Consumption
Note: Rising Edge response times are approximately double the Falling Edge response
times.
80
Rev. 1.4