C8051F52X_12 Datasheet, PDF (163/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
Table 16.1. SPI Slave Timing Parameters
Parameter
Description
Min
Master Mode Timing* (See Figure 16.6 and Figure 16.7)
T_MCKH
T_MCKL
T_MIS
T_MIH
SCK High Time
SCK Low Time
MISO Valid to SCK Sample Edge
SCK Sample Edge to MISO Change
1 x T_SYSCLK
1 x T_SYSCLK
20
0
Slave Mode Timing* (See Figure 16.8 and Figure 16.9)
T_SE
T_SD
T_SEZ
T_SDZ
T_CKH
T_CKL
T_SIS
T_SIH
T_SOH
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
2 x T_SYSCLK
2 x T_SYSCLK
—
—
5 x T_SYSCLK
5 x T_SYSCLK
2 x T_SYSCLK
2 x T_SYSCLK
—
Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK) in ns. 
The maximum possible frequency of the SPI can be calculated as:
Transmission: SYSCLK/2
Reception: SYSCLK/10
Max
Units
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
4 x T_SYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
Rev. 1.4
163