C8051F52X_12 Datasheet, PDF (94/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.1 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, IE, etc.) are bit-addressable
as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR
space are reserved for future use. Accessing these areas will have an indeterminate effect and should be
avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 9.2, for a detailed
description of each register.
Table 9.1. Special Function Register (SFR) Memory Map
F8 SPI0CN
PCA0L PCA0H PCA0CPL0 PCA0CPH0
VDDMON
F0
B
P0MDIN P1MDIN
EIP1
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
RSTSRC
E0
ACC
XBR0
XBR1
IT01CF
EIE1
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
D0 PSW
REF0CN
P0SKIP P1SKIP
P0MAT
C8 TMR2CN REG0CN TMR2RLL TMR2RLH TMR2L TMR2H
P1MAT
C0
ADC0GTL ADC0GTH ADC0LTL ADC0LTH P0MASK
B8
IP
ADC0TK ADC0MX ADC0CF ADC0L ADC0 P1MASK
B0 OSCIFIN OSCXCN OSCICN OSCICL
FLKEY
A8
IE
CLKSEL
A0
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT
98 SCON0
SBUF0
CPT0CN
CPT0MD
CPT0MX
90
P1
LINADDR LINDATA
LINCF
88 TCON
TMOD
TL0
TL1
TH0
TH1 CKCON PSCTL
80
P0
SP
DPL
DPH
PCON
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
(bit address-
able)
94
Rev. 1.4