C8051F52X_12 Datasheet, PDF (65/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFR Definition 4.5. ADC0CF: ADC0 Configuration
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
AD0SC
AD0RPT
GAINEN 11111000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xBC
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers
to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in
Table 2.3 on page 28.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the Burst Mode Oscillator, specified in Table 2.3.
AD0SC
=
---^F----^C----^L----^K----
CLK_SAR
–
1
*
or
CLK_SAR
=
-------^F----^C----^L----^K---------
AD0SC + 1
Note: Round the result up.
Bits2–1: AD0RPT1–0: ADC0 Repeat Count.
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert
start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single
convert start can initiate multiple self-timed conversions. Results in both modes are
accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are set to a value other
than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
Bit0:
GAINEN: Gain Enable Bit.
Controls the gain programming. For more information of the usage, refer to the following
chapter: Section “4.4. Selectable Gain” on page 60.
Rev. 1.4
65