C8051F52X_12 Datasheet, PDF (167/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
The following code programs the interface in Master mode, using the Enhanced Checksum and enables
the interface to operate at 19200 bits/sec using a 24 MHz system clock.
LIN0CF
LIN0CF
= 0x80;// Activate the interface
|= 0x40;// Set the node as a Master
LINADDR = 0x0D;// Point to the LIN0MUL register
// Initialize the register (prescaler, multiplier and bit 8 of divider)
LINDATA = ( 0x01 << 6 ) + ( 0x00 << 1 ) + ( ( 0x13F & 0x0100 ) >> 8 );
LINADDR = 0x0C;// Point to the LIN0DIV register
LINDATA = (unsigned char)_0x13F;// Initialize LIN0DIV
LINADDR = 0x0B;// Point to the LIN0SIZE register
LINDATA |= 0x80;// Initialize the checksum as Enhanced
LINADDR = 0x08;// Point to LIN0CTRL register
LINDATA = 0x0C;// Reset any error and the interrupt
Table 17.2 includes the configuration values required for the typical system clocks and baud rates:
SYSCLK
(MHz)
25
24.5
24
22.1184
16
12.25
12
11.0592
8
Table 17.2. Manual Baud Rate Parameters Examples
20 K
19.2 K
Baud (bits / sec)
9.6 K
4.8 K
0 1 312 0 1 325 1 1 325 3 1 325
0 1 306 0 1 319 1 1 319 3 1 319
0 1 300 0 1 312 1 1 312 3 1 312
0 1 276 0 1 288 1 1 288 3 1 288
0 1 200 0 1 208 1 1 208 3 1 208
0 0 306 0 0 319 1 0 319 3 0 319
0 0 300 0 0 312 1 0 312 3 0 312
0 0 276 0 0 288 1 0 288 3 0 288
0 0 200 0 0 208 1 0 208 3 0 208
1K
19 1 312
19 1 306
19 1 300
19 1 276
19 1 200
19 0 306
19 0 300
19 0 276
19 0 200
Rev. 1.4
167