C8051F52X_12 Datasheet, PDF (122/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
13.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 13.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which will be assigned to pins P0.4 and P0.5). If a Port pin is assigned, the
Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port
pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip
Port pins that are to be used for analog input, dedicated functions, or GPIO.
P0
P1
SF Signals
TSSOP 20 and QFN 20
PIN I/O
0123456701234567
TX0
C8051F53xA/F53x-C devices
RX0
TX0
C8051F53x devices
RX0
SCK
MISO
MOSI
NSS*
LIN-TX
LIN_RX
CP0
CP0A
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
0000000000000000
P0SKIP[0:7]
P1SKIP[0:7]
Port pin potentially assignable to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
Note: 4-Wire SPI Only.
Figure 13.3. Crossbar Priority Decoder with No Pins Skipped
(TSSOP 20 and QFN 20)
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P1.0 and/or P0.7 (F53x/F53xA) or
P0.2 and/or P0.3 (F52x/F52xA) for the external oscillator, P0.0 for V_REF, P1.2 (F53x/F53xA) or P0.5
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Rev. 1.4