C8051F52X_12 Datasheet, PDF (211/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
First character of
the trace code
identifies the
silicon revision
Figure 20.3. Device Package—DFN 10
20.2. Reset Pin Behavior
The reset behavior differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA devices. The dif-
ferences affect the state of the RST pin during a VDD Monitor reset.
On Revision A devices, a V_DD Monitor reset does not affect the state of the RST pin. On Revision B and
Revision C devices, a V_DD Monitor reset will pull the RST pin low for the duration of the brownout condi-
tion.
20.3. Reset Time Delay
The reset time delay differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA devices.
On Revision A devices, the reset time delay will be as long as 80 ms following a power-on reset, meaning
it can take up to 80 ms to begin code execution. Subsequent resets will not cause the long delay. On Revi-
sion B and Revision C devices, the startup time is around 350 µs, specified as T_PORDELAY in Table 2.8,
“Reset Electrical Characteristics,” on page 32.
20.4. V_DD Monitors and V_DD Ramp Time
The number of V_DD monitors and definition of “V_DD ramp time” differs between the silicon revisions of
C8051F52x/52xA/F53x/F53xA devices.
On Revision A and Revision B devices, the only V_DD monitor present is the standard V_DD monitor
(VDDMON0). On these devices, the V_DD ramp time is defined as how fast V_DD ramps from 0 V to V_RST.
Here, V_RST is the V_RST-LOW threshold of VDDMON0 specifed in Table 2.8, “Reset Electrical Characteris-
tics,” on page 32. The maximum V_DD ramp time for these devices is 1 ms; slower ramp times may cause
the device to be released from reset before V_DD reaches the V_RST-LOW level.
Revision C devices include two V_DD monitors: a standard V_DD monitor (VDDMON0) and a level-sensitive
V_DD monitor (VDDMON1). See Section 11.2 on page 108 for more details. On these devices, the V_DD
ramp time is defined as how fast V_DD ramps from 0 V to V_RST1. V_RST1 is specified in Table 2.8, “Reset
Electrical Characteristics,” on page 32 as the threshold of the new level-sensitive V_DD monitor
(VDDMON1). This new V_DD monitor will hold the device in reset until V_DD reaches the V_RST1 level irre-
spective of the length of the V_DD ramp time.
Note: Please refer to Section “11.2.1. VDD Monitor Thresholds and Minimum VDD” on page 108 for
recommendations related to minimum V_DD.
Rev. 1.4
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