C8051F52X_12 Datasheet, PDF (219/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
 Replaced minimum VDD value for Flash write/erase operations in Table 2.9 on page 33 with references
to the V_RST-HIGH theshold specified in Table 2.8 on page 32.
 Removed Output Low Voltage values for condition ‘V_REGIN = 1.8 V’ from Table 2.10, “Port I/O DC
Electrical Characteristics,” on page 33.
 Corrected minor typo (“IFCN = 111b”) in Table 2.11, “Internal Oscillator Electrical Characteristics,” on
page 34.
 Removed the typical value and added the maximum value for the 'Wake-up Time From Suspend'
specification with the 'ZTCEN = 0' condition in Table 2.11, “Internal Oscillator Electrical Characteristics,”
on page 34.
 Added Internal Oscillator Supply current values at specific temperatures for conditions ‘ZTCEN = 1’ and
‘ZTCEN = 0’ in Table 2.11, “Internal Oscillator Electrical Characteristics,” on page 34. Also updated the
table name to clarify that the specifications apply to the internal oscillator.
 Updated Section “1.1. Ordering Information” on page 14 and Table 1.1 with new C8051F52x-C/F53x-C
part numbers.
 Updated Table 1.2, “Product Selection Guide (Not Recommended for New Designs),” on page 15 to
include C8051F52xA/F53xA part numbers.
 Updated Figure 1.1, Figure 1.2, Figure 1.3, and Figure 1.4 titles to clarify applicable silicon revisions.
 Added figure references to pinout diagrams (Figure 3.1, Figure 3.4, and Figure 3.7) and updated labels
to clarify applicable part numbers.
 Updated Table 3.1, Table 3.4, and Table 3.7 to indicate pinouts applicable to C8051F52x-C/F53x-C
devices.
 Added note in Section “6. Voltage Regulator (REG0)” on page 74 to indicate the need for bypass
capacitors for voltage regulator stability.
 Updated Figure 11.1 on Page 106 and text in Section “11.1. Power-On Reset” on page 107 and Section
“11.2. Power-Fail Reset / VDD Monitors (VDDMON0 and VDDMON1)” on page 108 to describe the
new level-sensitive V_DD monitor (VDDMON1).
 Updated SFR Definition 11.1. “VDDMON: VDD Monitor Control” on page 109 to include the VDM1EN
bit (bit 4) that controls the new level-sensitive V_DD monitor (VDDMON1).
 Added notes in Section 11.1 on page 107, Section 11.2 on page 108, and Section 11.3 on page 110
with references to relevant parts of Section “20. Device Specific Behavior” on page 210.
 Moved some notes related to VDD Monitor (VDDMON0) High Threshold setting (V_RST-HIGH) from
Section 11.2 on page 108 to Section 20.5 on page 212 in Section “20. Device Specific Behavior”.
 Added Section “11.2.1. VDD Monitor Thresholds and Minimum VDD” on page 108 to describe the
recommendations for minimum V_DD as it relates to the V_DD monitor thresholds.
 Clarified text in Section “11.7. Flash Error Reset” on page 110.
 Clarified text in items 2, 3 and 4 in Section “12.2.1. V_DD Maintenance and the V_DD monitor” on page 115
to reference appropriate specification tables and specify “VDDMON0”.
Rev. 1.4
219