C8051F52X_12 Datasheet, PDF (170/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
17.4. LIN Slave Mode Operation
When the device is configured for slave mode operation, it must wait for a command from a master node.
Access from the firmware to data buffer and ID registers of the LIN peripheral is only possible when a data
request is pending (DTREQ bit (LIN0ST.4) is 1) and also when the LIN bus is not active (ACTIVE bit
(LIN0ST.7) is set to 0).
The LIN peripheral in slave mode detects the header of the message frame sent by the LIN master. If slave
synchronization is enabled (autobaud), the slave synchronizes its internal bit time to the master bit time.
The LIN peripheral configured for slave mode will generated an interrupt in one of three situations:
1. After the reception of the IDENTIFIER FIELD.
2. When an error is detected.
3. When the message transfer is completed.
The application should perform the following steps when an interrupt is detected:
1. Check the status of the DTREQ bit (LIN0ST.4). This bit is set when the IDENTIFIER FIELD has been
received.
2. If DTREQ (LIN0ST.4) is set, read the identifier from LIN0ID and process it. If DTREQ (LIN0ST.4) is not
set, continue to step 7.
3. Set the TXRX bit (LIN0CTRL.5) to 1 if the current frame is a transmit operation for the slave and set to
0 if the current frame is a receive operation for the slave.
4. Load the data length into LIN0SIZE.
5. For a slave transmit operation, load the data to transmit into the data buffer.
6. Set the DTACK bit (LIN0CTRL.4). Continue to step 10.
7. If DTREQ (LIN0ST.4) is not set, check the DONE bit (LIN0ST.0). The transmission was successful if the
DONE bit is set.
8. If the transmission was successful and the current frame was a receive operation for the slave, load the
received data bytes from the data buffer.
9. If the transmission was not successful, check LIN0ERR to determine the nature of the error. Further
error handling has to be done by the application.
10.Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
error flags.
In addition to these steps, the application should be aware of the following:
1. If the current frame is a transmit operation for the slave, steps 1 through 5 must be completed during
the IN-FRAME RESPONSE SPACE. If it is not completed in time, a timeout will be detected by the
master.
2. If the current frame is a receive operation for the slave, steps 1 through 5 have to be finished until the
reception of the first byte after the IDENTIFIER FIELD. Otherwise, the internal receive buffer of the LIN
peripheral will be overwritten and a timeout error will be detected in the LIN peripheral.
3. The LIN module does not directly support LIN Version 1.3 Extended Frames. If the application detects
an unknown identifier (e.g. extended identifier), it has to write a 1 to the STOP bit (LIN0CTRL.7) instead
of setting the DTACK (LIN0CTRL.4) bit. At that time, steps 2 through 5 can then be skipped. In this
situation, the LIN peripheral stops the processing of the LIN communication until the next SYNC
BREAK is received.
4. Changing the configuration of the checksum during a transaction will cause the interface to reset and
the transaction to be lost. To prevent this, the checksum should not be configured while a transaction is
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Rev. 1.4