C8051F52X_12 Datasheet, PDF (123/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
(F52x/F52xA) for the external CNVSTR signal, and any selected ADC or comparator inputs. The Crossbar
skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 13.3
shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP); Figure 13.4 shows the
Crossbar Decoder priority with the XTAL1 (P1.0) and XTAL2 (P1.1) pins skipped (P1SKIP = 0x03).
Important Note on UART Pins: On C8051F52xA/F52x-C/F53xA/F53x-C devices, the UART pins must be
skipped if the UART is enabled in order for peripherals to appear on port pins beyond the UART on the
crossbar. For example, with the SPI and UART enabled on the crossbar with the SPI on P1.0-P1.3, the
UART pins must be skipped using P0SKIP for the SPI pins to appear correctly.
P0
P1
SF Signals
TSSOP 20 and QFN 20
PIN I/O
TX0
RX0
TX0
RX0
SCK
MISO
MOSI
NSS*
LIN-TX
LIN-RX
CP0
CP0A
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
01234567012 34567
C8051F53xA/F53x-C
devices
C8051F53x devices
00000001100 00000
P0SKIP[0:7] = 0x80
P1SKIP[0:7] = 0x01
Port pin potentially assignable to peripheral
SF Signals
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the Crossbar must be manually configured
to skip their corresponding port pins.
Note: 4-Wire SPI Only.
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped
(TSSOP 20 and QFN 20)
Rev. 1.4
123