C8051F52X_12 Datasheet, PDF (113/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
12. Flash Memory
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX
write instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase
operations is not required. Code execution is stalled during Flash write/erase operations. Refer to
Table 2.9 on page 33 for complete Flash memory electrical characteristics.
12.1. Programming The Flash Memory
The simplest means of programming the Flash memory is through the C2 interface using programming
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a
non-initialized device. For details on the C2 commands to program Flash memory, see Section “21. C2
Interface” on page 214.
To protect the integrity of Flash contents, the V_DD monitor must be enabled to the higher setting
(VDMLVL = '1') and selected as a reset source if software contains routines which erase or write Flash
memory. If the V_DD monitor is not enabled, any erase or write performed on Flash memory will cause a
Flash Error device reset. See Section “11.2. Power-Fail Reset / VDD Monitors (VDDMON0 and
VDDMON1)” on page 108 for more information regarding the VDD monitor and the high threshold setting.
The V_DD monitor must be enabled before it is selected as a reset source. Selecting the V_DD monitor
as a reset source before it is enabled and stabilized may cause a system reset. The procedure for re-
enabling the V_DD monitor and configuring the V_DD monitor as a reset source is shown below:
1. Enable the V_DD monitor (VDMEN bit in VDDMON = 1).
2. Wait for the V_DD monitor to stabilize (see Table 2.8 on page 32 for the V_DD Monitor turn-on time). Note:
This delay should be omitted if software contains routines which write or erase Flash memory.
3. Select the V_DD monitor as a reset source (PORSF bit in RSTSRC = 1).
Note: 8-bit MOVX instructions cannot be used to erase or write to Flash memory at addresses higher than
0x00FF.
Important Note: For –I (industrial Grade) parts, flash should be programmed (erase/write) at a mini-
mum temperature of 0 °C for reliable flash operation across the entire temperature range of –40 to
+125 °C. This minimum programming temperature does not apply to –A (Automotive Grade) parts.
12.1.1. Flash Lock and Key Functions
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash
write or erase is attempted before the key codes have been written properly. The Flash lock resets after
each write or erase; the key codes must be written again before a following Flash operation can be per-
formed. The FLKEY register is detailed in SFR Definition 12.2.
Rev. 1.4
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