C8051F52X_12 Datasheet, PDF (190/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
18.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the RTC0 clock fre-
quency or the External Oscillator clock frequency.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external oscillator source divided by 8 is synchronized with the system clock.
18.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 18.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
T2XCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
SYSCLK / 12
0
External Clock / 8
1
SYSCLK
0
TR2
1
TMR2L
Overflow
TCLK _TMR2L
TMR2H
TMR2RLL TMR2RLH
Reload
TF2H
TF2L
TF2LEN
T2SPLIT
TR2
T2XCLK
Interrupt
Figure 18.4. Timer 2 16-Bit Mode Block Diagram
190
Rev. 1.4