C8051F52X_12 Datasheet, PDF (180/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFR Definition 17.15. LIN0SIZE: LIN0 Message Size Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ENHCHK
-
-
-
LINSIZE[3:0]
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R/W
Reset Value
00000000
Bit0
Address: 0x0B (indirect)
Bit7:
Bit6–4:
Bit3–0:
ENHCHK: Checksum Selection Bit.
0: Use the classic, specification 1.3 compliant checksum. Checksum covers the data bytes.
1: Use the enhanced, specification 2.1 compliant checksum. Checksum covers data bytes
and protected identifier.
UNUSED. Read = 000b. Write = don’t care.
LINSIZE3–0: Data Field Size.
0000: 0 data bytes
0001: 1 data byte
0010: 2 data bytes
0011: 3 data bytes
0100: 4 data bytes
0101: 5 data bytes
0110: 6 data bytes
0111: 7 data bytes
1000: 8 data bytes
1001-1110: RESERVED
1111: Use the ID[1:0] bits (LIN0ID[5:4]) to determine the data length.
SFR Definition 17.16. LIN0DIV: LIN0 Divider Register
R
R
R
R
R
R
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R
Reset Value
00000000
Bit0
Address: 0x0C (indirect)
Bit7–0: DIVLSB[7:0]: LIN Baud Rate Divider Least Significant Bits.
The 8 least significant bits for the baud rate divider. The 9th and most significant bit is the
DIV9 bit (LIN0MUL.0). The valid range for the divider is 200 to 511.
180
Rev. 1.4