C8051F52X_12 Datasheet, PDF (28/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
Table 2.3. ADC0 Electrical Characteristics
V_DD = 2.1 V, V_REF = 1.5 V (REFSL=0), –40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
—
—
±3
LSB
Differential Nonlinearity
Offset Error¹
Guaranteed Monotonic
—
—
±1
LSB
–10 ±1
+10
LSB
Full Scale Error
–20 ±1
+20
LSB
Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Up to the 5^th harmonic
60
66
—
dB
—
74
—
dB
Spurious-Free Dynamic Range
—
88
—
dB
Conversion Rate
SAR Conversion Clock
Burst Mode Oscillator
Conversion Time in SAR Clocks²
Track/Hold Acquisition Time^3,6
Throughput Rate⁴
—
—
3
MHz
—
—
27
MHz
—
13
—
clocks
1
—
—
µs
—
—
200
ksps
Analog Inputs
ADC Input Voltage Range⁵
Absolute Pin Voltage wrt to GND
Sampling Capacitance
Input Multiplexer Impedance
gain = 1.0 (default)
gain = n
0
—
V_REF
V
0
— V_REF / n
0
—
V_REGIN
V
—
24
—
pF
—
1.5
—
k
Power Specifications
Power Supply Current (from VDD)
Burst Mode (Idle)
Power-on Time
Power Supply Rejection
Operating Mode, 200 ksps
— 1050 1400
µA
— 930
—
µA
—
5
—
µs
—
1
—
mV/V
Notes:
1. Represents one standard deviation from the mean. Offset and full-scale error can be removed through
calibration.
2. An additional 2 FCLK cycles are required to start and complete a conversion.
3. Additional tracking time may be required depending on the output impedance connected to the ADC input.
See Section “4.3.6. Settling Time Requirements” on page 60.
4. An increase in tracking time will decrease the ADC throughput.
5. See Section “4.4. Selectable Gain” on page 60 for more information about setting the gain.
6. Additional tracking time might be needed ifVDD < 2.0 V; See Section “11.2.1. VDD Monitor Thresholds and
Minimum VDD” on page 108 for minimum V_DD requirements.
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Rev. 1.4