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C8051F52X_12 Datasheet, PDF (218/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family | |||
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C8051F52x/F53x
Revision 1.2 to 1.3
ï® Updated âSystem Overviewâ on page 13 with a voltage range specification for the internal oscillator.
ï® Updated Table 2.11 on page 34 with new conditions for the internal oscillator accuracy. The internal
oscillator accuracy is dependent on the operating voltage range.
ï® Updated Section 2 to remove the internal oscillator curve across temperature diagram.
ï® Updated Figure â4.5 12-Bit ADC Burst Mode Example with Repeat Count Set to 4â on page 58 with new
timing diagram when using CNVSTR pin.
ï® Updated SFR Definition 5.1 (REF0CN) with oscillator suspend requirement for ZTCEN.
ï® Updated SFR Definition 6.1 (REG0CN) with a new definition for Bit 6. The bit 6 reset value is 1b and
must be written to 1b.
ï® Updated Section â8.3.3. Suspend Modeâ on page 90 with note regarding ZTCEN.
ï® Updated Section â17. LIN (C8051F520/0A/3/3A/6/6A and C8051F530/0A/3/3A/6/6A)â on page 164 with
a voltage range specification for the internal oscillator.
Revision 1.3 to 1.4
ï® Added âAEC-Q100â qualification information on page 1.
ï® Changed page headers throughout the document from âC8051F52x/F52xA/F53x/F53xAâ to
âC8051F52x/53xâ.
ï® Updated supply voltage to "2.0 to 5.25 V" on page 1 and in Section 1 on page 13.
ï® Corrected reference to development kit (C8051F530DK) in Section â1.2.4. On-Chip Debug Circuitryâ on
page 18.
ï® Updated minimum Supply Input Voltage (VREGIN) for C8051F52x-C/F53x-C devices in Table 2.2 on
page 26 and Table 2.6 on page 30.
ï® Updated digital supply current (IDD and Idle IDD) typical values for condition âClock = 25 MHzâ in
Table 2.2 on page 26.
ï® Updated IDD Frequency Sensitivity and Idle IDD Frequency Sensitivity values in Table 2.2 on page 26;
removed Figure 2.1 and Figure 2.2 that used to provide the same frequency sensitivity slopes. Also
removed IDD Supply Sensitivity and Idle IDD Supply Sensitivity typical values.
ï® Added Digital Supply Current (Stop or Suspend Mode) values at multiple temperatures Table 2.2 on
page 26.
ï® Added a note in Table 2.3, âADC0 Electrical Characteristics,â on page 28 with reference to Section
â4.4. Selectable Gainâ on page 60; also added note to indicate that additional tracking time may be
necessary if VDD is less than the minimum specified VDD.
ï® Split off temperature sensor specifications from Table 2.3 into a separate table Table 2.4; Updated
temperature sensor gain and added supply current values.
ï® Added temperature condition for Bias Current specification in Table 2.6 on page 30.
ï® Updated Comparator Input Offset Voltage values in Table 2.7 on page 31.
ï® Updated VDD Monitor (VDDMON0) Low Threshold (VRST-LOW) minimum value for C8051F52xA/F52x-
C/F53xA/F53x-C devices in Table 2.8 on page 32.
ï® Updated VDD Monitor (VDDMON0) supply current values in Table 2.8 on page 32.
ï® Added specifications for the new level-sensitive VDD monitor (VDDMON1) to Table 2.8, âReset
Electrical Characteristics,â on page 32 and also added notes to clarify the applicable VRST theshold
level.
ï® Added note in Table 2.9, âFlash Electrical Characteristics,â on page 33 to describe the minimum flash
programming temperature for âI (Industrial Grade) devices; Also added the same note and references
to it in Section â12.1. Programming The Flash Memoryâ on page 113, Section â12.3. Non-volatile Data
Storageâ on page 117, and in SFR Definition 12.1 (PSCTL).
218
Rev. 1.4
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