C8051F52X_12 Datasheet, PDF (178/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
SFR Definition 17.13. LIN0ST: LIN0 STATUS Register
R
ACTIVE
Bit7
R
IDLTOUT
Bit6
R
ABORT
Bit5
R
DTREQ
Bit4
R/W
LININT
Bit3
R
R
ERROR WAKEUP
Bit2
Bit1
R
Reset Value
DONE
00000000
Bit0
Address: 0x09 (indirect)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
ACTIVE: LIN Bus Activity Bit.
0: No transmission activity detected on the LIN bus.
1: Transmission activity detected on the LIN bus.
IDLTOUT: Bus Idle Timeout Bit (slave mode only).
0: The bus has not been idle for four seconds.
1: No bus activity has been detected for four seconds, but the bus is not yet in Sleep mode.
ABORT: Aborted transmission signal (slave mode only).
0: The current transmission has not been interrupted or stopped. This bit is reset to 0 after
receiving a SYNCH BREAK that does not interrupt a pending transmission.
1: New SYNCH BREAK detected before the end of the last transmission or the STOP bit
(LIN0CTRL.7) has been set.
DTREQ: Data Request bit (slave mode only).
0: Data identifier has not been received.
1: Data identifier has been received.
LININT: Interrupt Request bit.
0: An interrupt is not pending. This bit is cleared by setting RSTINT (LIN0CTRL.3)
1: There is a pending LIN0 interrupt.
ERROR: Communication Error Bit.
0: No error has been detected. This bit is cleared by setting RSTERR (LIN0CTRL.2)
1: An error has been detected.
WAKEUP: Wakeup Bit.
0: A wakeup signal is not being transmitted and has not been received.
1: A wakeup signal is being transmitted or has been received.
DONE: Transmission Complete Bit.
0: A transmission is not in progress or has not been started. This bit is cleared at the start of
a transmission.
1: The current transmission is complete.
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Rev. 1.4