C8051F52X_12 Datasheet, PDF (61/221 Pages) Silicon Laboratories – 8/4/2 kB ISP Flash MCU Family

C8051F52x/F53x
4.4.1. Calculating the Gain Value
The ADC0 selectable gain feature is controlled by 13 bits in three registers. ADC0GNH contains the 8
upper bits of the gain value and ADC0GNL contains the 4 lower bits of the gain value. The final GAINADD
bit (ADC0GNA.0) controls an optional extra 1/64 (0.016) of gain that can be added in addition to the
ADC0GNH and ADC0GNL gain. The ADC0GNA.0 bit is set to 1 after a power-on reset.
The equivalent gain for the ADC0GNH, ADC0GNL and ADC0GNA registers is:
gain
=


G_--4---0A_---9-I_--6-N_{--}
+
GAI
NADD



6--1-4--^
Equation 4.2. Equivalent Gain from the ADC0GNH and ADC0GNL Registers
Where:
GAIN is the 12-bit word of ADC0GNH[7:0] and ADC0GNL[7:4]
GAINADD is the value of the GAINADD bit (ADC0GNA.0)
gain is the equivalent gain value from 0 to 1.016
For example, if ADC0GNH = 0xFC, ADC0GNL = 0x00, and GAINADD = '1', GAIN = 0xFC0 = 4032, and
the resulting equation is:
gain
=


44----00---39---26-_
+
1



6--1--4-^
=
0.984 + 0.016
=
1.0
The table below equates values in the ADC0GNH, ADC0GNL, and ADC0GNA registers to the equivalent
gain using this equation.
ADC0GNH Value
0xFC (default)
0x7C
0xBC
0x3C
0xFF
0xFF
ADC0GNL Value
0x00 (default)
0x00
0x00
0x00
0xF0
0xF0
GAINADD Value
1 (default)
1
1
1
0
1
GAIN Value
4032 + 64
1984 + 64
3008 + 64
960 + 64
4095 + 0
4095 + 64
Equivalent Gain
1.0 (default)
0.5
0.75
0.25
~1.0
1.016
For any desired gain value, the GAIN registers can be calculated by:
GAIN = _gain – GAINADD  _{6--1--4-}  4096
Equation 4.3. Calculating the ADC0GNH and ADC0GNL Values from the Desired Gain
Where:
GAIN is the 12-bit word of ADC0GNH[7:0] and ADC0GNL[7:4]
GAINADD is the value of the GAINADD bit (ADC0GNA.0)
gain is the equivalent gain value from 0 to 1.016
When calculating the value of GAIN to load into the ADC0GNH and ADC0GNL registers, the GAINADD bit
can be turned on or off to reach a value closer to the desired gain value.
Rev. 1.4
61