HD64F7144F50V Datasheet, PDF (91/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2.6 Processing States
2. CPU
2.6.1 State Transitions
The CPU has five processing states: reset, exception processing, bus release, program execution
and power-down. Figure 2.4 shows the transitions between the states.
From any state
when RES = 0
From any state when
RES = 1, MRES = 0,
Power-on reset state
RES = 0
Manual reset state
When an internal power-on
reset by WDT or internal manual reset by
WDT occurs
Interrupt sources generated
or DMAC/DTC address
error occurs*
Bus request
cleared
RES = 1
Exception
processing state
RES = 1,
MRES = 1
Bus request
generated
Exception
processing
source
occurs
Exception
processing
ends
Bus release state
Bus request
cleared
Bus request
generated
Program execution state
Reset state
NMI or IRQ interrupt
source occurs
Bus request Bus request
generated
cleared
SSBY bit cleared
for SLEEP
instruction
SSBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Power-down state
Note: * Enabled only in masked ROM version and ROM less version. Disabled in F-ZTAT version and emulator.
Figure 2.4 Transitions between Processing States
Rev.4.00 Mar. 27, 2008 Page 45 of 882
REJ09B0108-0400