HD64F7144F50V Datasheet, PDF (529/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. I²C Bus Interface (IIC) Option
Table 14.4 The Relationship between Flags and Transfer States (Master Mode)
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State
1 1 0 0 0 0 0↓ 0 0↓ 0↓ 0
⎯
0
Idle state (flag clearing
required)
1 1 1↑ 0 0 1↑ 0 0 0 0 0
⎯ 1↑
Start condition detected
1 ⎯ 1 0 0 ⎯ 0 00 0 ⎯ ⎯ ⎯
Wait state
1 1 1 0 0 ⎯ 0 0 0 0 1↑ ⎯ ⎯
Transmission end (ACKE = 1
and ACKB = 1)
1 1 1 0 0 1↑ 0 0 0 0 0
⎯ 1↑
Transmission end with
ICDRE = 0
1 1 1 0 0 ⎯ 0 00 0 0
⎯
0↓
ICDR write with the above
state
1 1 1 0 0 ⎯ 0 00 0 0
⎯
1
Transmission end with
ICDRE = 1
1 1 1 0 0 ⎯ 0 00 0 0
⎯
0↓
ICDR write with the above
state or after start condition
detected
1 1 1 0 0 1↑ 0 0 0 0 0
⎯ 1↑
Automatic data transfer from
ICDRT to ICDRS with the
above state
1 0 1 0 0 1↑ 0 0 0 0 ⎯ 1↑ ⎯
Reception end with ICDRF =
0
1 0 1 0 0 ⎯ 0 0 0 0 ⎯ 0↓ ⎯
ICDR read with the above
state
1 0 1 0 0 ⎯ 0 00 0 ⎯ 1
⎯
Reception end with ICDRF =
1
1 0 1 0 0 ⎯ 0 0 0 0 ⎯ 0↓ ⎯
ICDR read with the above
state
1 0 1 0 0 1↑ 0 0 0 0 ⎯ 1↑ ⎯
Automatic data transfer from
ICDRS to ICDRR with the
above state
0↓ 0↓ 1 0
0
⎯0
1↑ 0 0 ⎯
⎯
⎯
Arbitration lost
1 ⎯ 0↓ 0 0 ⎯ 0 0 0 0 ⎯ ⎯ 0↓
Stop condition detected
[Legend]
0:
0-state retained
1:
1-state retained
⎯: Previous state retained
0↓: Cleared to 0
1↑: Set to 1
Rev.4.00 Mar. 27, 2008 Page 483 of 882
REJ09B0108-0400