HD64F7144F50V Datasheet, PDF (126/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Interrupt Controller (INTC)
6.3.1 Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input
pins NMI and IRQ0 to IRQ7 and indicates the input signal level at the NMI pin.
Bit
Bit Name Initial Value R/W
15
NMIL
1/0
R
14 to 9 —
All 0
R
8
NMIE
0
R/W
7
IRQ0S 0
R/W
6
IRQ1S 0
R/W
5
IRQ2S 0
R/W
Description
NMI Input Level
Sets the level of the signal input to the NMI pin. This
bit can be read to determine the NMI pin level. This bit
cannot be modified.
0: NMI input level is low
1: NMI input level is high
Reserved
These bits are always read as 0. The write value
should always be 0.
NMI Edge Select
0: Interrupt request is detected on falling edge of NMI
input
1: Interrupt request is detected on rising edge of NMI
input
IRQ0 Sense Select
This bit sets the IRQ0 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ0
input
1: Interrupt request is detected on edge of IRQ0 input
(edge direction is selected by ICR2)
IRQ1 Sense Select
This bit sets the IRQ1 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ1
input
1: Interrupt request is detected on edge of IRQ1 input
(edge direction is selected by ICR2)
IRQ2 Sense Select
This bit sets the IRQ2 interrupt request detection
mode.
0: Interrupt request is detected on low level of IRQ2
input
1: Interrupt request is detected on edge of IRQ2 input
(edge direction is selected by ICR2)
Rev.4.00 Mar. 27, 2008 Page 80 of 882
REJ09B0108-0400