HD64F7144F50V Datasheet, PDF (231/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Direct Memory Access Controller (DMAC)
Transfer on channel 0
Initial priority setting _{CH0 > CH1 > CH2 > CH3}
Channel 0 is given the lowest
priority.
Priority after transfer
CH1 > CH2 > CH3 > CH0
Transfer on channel 1
Initial priority setting
Priority after transfer
CH0 > CH1 > CH2 > CH3
CH2 > CH3 > CH0 > CH1
When channel 1 is given the
lowest priority, the priority
of channel 0, which was
above channel 1, is also shifted
simultaneously.
Transfer on channel 2
Initial priority setting CH0 > CH1 > CH2 > CH3
Priority after transfer
CH3 > CH0 > CH1 > CH2
Priority after transfer
due to issue of a transfer
request for channel 1
only.
CH2 > CH3 > CH0 > CH1
When channel 2 receives the
lowest priority, the priorities
of channel 0 and 1, which
were above channel 2, are also
shifted simultaneously. Immedi-
ately thereafter, if there is a transfer
request for channel 1 only, channel
1 is given the lowest priority,
and the priorities of channels 3
and 0 are simultaneously
shifted down.
Transfer on channel 3
Initial priority setting _{CH0 > CH1 > CH2 > CH3}
No change in priority.
Priority after transfer _{CH0 > CH1 > CH2 > CH3}
Figure 10.3 (1) Round Robin Mode
Rev.4.00 Mar. 27, 2008 Page 185 of 882
REJ09B0108-0400