HD64F7144F50V Datasheet, PDF (456/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
2 TEND
1
R
Transmit End
Indicates that transmission has been ended.
[Setting conditions]
• Power-on reset or software standby mode
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE =
1
• When the DMAC is activated by a TXI interrupt
request.
• When the DTC is activated by a TXI interrupt and
transmit data is written to TDR while the DISEL
bit in DTMR of DTC is 0.
1 MPB
0
R
Multiprocessor Bit
Stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0, its previous
state is retained.
0 MPBT
0
R/W Multiprocessor Bit Transfer
Sets the multiprocessor bit value to be added to the
transmit data.
Note: * Only 0 can be written to clear the flag.
Rev.4.00 Mar. 27, 2008 Page 410 of 882
REJ09B0108-0400