HD64F7144F50V Datasheet, PDF (909/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

D. I/O Port Block Diagrams
AUDATA0 (AUD)
SCK3 (SCI)
TIOC2A (MTU)
RES
R
Q PE6DR D
C
PEDRL.WR
PEDRL.RD
TIOC2A (MTU)
SCK3 (SCI)
AUDATA0 (AUD)
PFC
Q PE6MD0
Q PE6MD1
Q PE6IOR
AUDSYNC
AUD reset
AUDMD
SBYCR
Q Hi-Z
Software standby
AUD module standby
RES: Reset signal
PEDRL.RD: Port E data register L read signal
PEDRL.WR: Port E data register L write signal
Figure D.51 PE6/TIOC2A/SCK3/AUDATA0
Pins
PE6/TIOC2A/
SCK3/
AUDATA0
Symbol in Figure D.51
Available Products
SH7144
SH7145
Masked ROM
Masked ROM
version/
version/
F-ZTAT ROM less
F-ZTAT ROM less
PE6 TIOC2A SCK3 AUDATA0 _{version version}
version version
PE6 TIOC2A SCK3 AUDATA0 ⎯
⎯
(MTU) (SCI) (AUD)
√
⎯
Rev.4.00 Mar. 27, 2008 Page 863 of 882
REJ09B0108-0400