HD64F7144F50V Datasheet, PDF (677/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

17. Pin Function Controller (PFC)
17.2 Usage Notes
1. In this LSI, the same function is available as a multiplexed function on multiple pins. This
approach is intended to increase the number of selectable pin functions and to allow the easier
design of boards. If two or more pins are specified for one function, however, there are two
cautions shown below.
⎯ When the pin function is input
Signals input to several pins are formed as one signal through OR or AND logic and the
signal is transmitted into the LSI. Therefore, a signal that differs from the input signals may
be transmitted to the LSI depending on the input signals in other pins that have the same
functions. Table 17.15 shows the transmit forms of input functions allocated to several
pins. When using one of the functions shown below in multiple pins, use it with care of
signal polarity considering the transmit forms.
Table 17.15 Transmit Forms of Input Functions Allocated to Multiple Pins
Product
SH7144
SH7145
OR Type
SCK3, RXD3
SCK3, RXD3, AUDMD*,
AUDATA0 to AUDATA3*
Note: * F-ZTAT version only
AND Type
IRQ0 to IRQ3, DREQ0, DREQ1
IRQ0 to IRQ7, DREQ0, DREQ1,
BREQ, WAIT, ADTRG, AUDRST*,
AUDSYNC*, AUDCK*
OR type: Signals input to several pins are formed as one signal through OR logic and the
signal is transmitted into the LSI.
AND type: Signals input to several pins are formed as one signal through AND logic and
the signal is transmitted into the LSI.
⎯ When the pin function is output
Each selected pin can output the same function.
2. When the port input is switched from a low level to the DREQ or the IRQ edge for the pins
that are multiplexed with input/output and DREQ or IRQ, the corresponding edge is detected.
3. Do not set functions other than those specified in tables 17.13 and 17.14. Otherwise, correct
operation cannot be guaranteed.
4. When pin functions are selected, set the port I/O registers (PBIOR and PDIORL) after setting
the port control registers (PBCR1, PBCR2, PDCRL1, and PDCRL2).
However, when selecting pin functions that are multiplexed with port A, port C, PD31 to PD16
of port D, and port E, no strict attention is required in setting the order of port control registers
(PACRH, PACRL1, PACRL2, PCCR, PDCRH1, PDCRH2, PECRL1, and PECRL2) and port
I/O registers (PAIORH, PAIORL, PCIOR, PDIORH, and PEIORL).
Rev.4.00 Mar. 27, 2008 Page 631 of 882
REJ09B0108-0400