HD64F7144F50V Datasheet, PDF (55/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

1. Overview
Type
System
control
Symbol
RES
MRES
WDTOVF
I/O
Input
Input
Output
BREQ
BACK
Input
Output
Interrupts
NMI
Input
IRQ7 to IRQ0 Input
IRQOUT
Output
Address bus A21 to A0
Data bus
SH7144:
D15 to D0
SH7145:
D31 to D0
Output
Input/
Output
Name
Function
Power on
reset
When this pin is driven low, the chip
becomes to power on reset state.
Manual reset When this pin is driven low, the chip
becomes to manual reset state.
Watchdog
timer overflow
Output signal for the watchdog timer
overflow.
If this pin needs to be pulled-down, the
resistance value must be 1 MΩ or higher.
Bus request External device can request the release of
the bus mastership by setting this pin low.
Bus
acknowledge
Shows that the bus mastership has been
released for the external device. The
device that had issued the BREQ signal
can know that bus mastership has been
released for itself by receiving the BACK
signal.
Non-maskable Non-maskable interrupt pin. If this pin is
interrupt
not used, it should be fixed high or low.
Interrupt
request 7 to 0
These pins request a maskable interrupt.
One of the level input or edge input can be
selected In case of the edge input, one of
the rising edge, falling edge, or both can
be selected.
Interrupt
Shows that an interrupt cause has
request output occurred. The interrupt cause can be
recognized even in the bus release state.
Address bus Output the address.
Data bus
SH7144: Bi-directional 16-bit bus
SH7145: Bi-directional 32-bit bus
Rev.4.00 Mar. 27, 2008 Page 9 of 882
REJ09B0108-0400