HD64F7144F50V Datasheet, PDF (584/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. I²C Bus Interface (IIC) Option
13. Points for cautions when setting TRS bit in slave mode
In I²C bus interface slave mode, the value set to the TRS bit in ICCR immediately becomes
valid if it is set from the time when the rising edge of the 9th cycle or the stop condition is
detected until the time when the next rising edge on the SCL pin is detected (the period
indicated as (a) in figure 14.35).
However, if the TRS bit is set outside the period mentioned above (the period indicated as (b)
in figure 14.35), the bit value does not become valid immediately because it is suspended until
the rising edge of the 9th cycle or the stop condition is detected. Therefore, when the address is
received after the re-transmission start condition input without the stop condition, the effective
TRS bit value remains 1 (transmit mode) internally and thus the acknowledge bit is not
transmitted after the address has been received at the 9th cycle of the clock.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 14.35.
To release SCL low-level fixation that is held by means of the wait function in slave mode,
clear the TRS bit to 0 and then dummy-read ICDR.
Resumption condition
(a)
(b)
SDA
A
SCL
89
123 456 789
TRS Data
transmission
Address reception
Period in which TRS bit setting is retained
ICDR dummy read
TRS bit setting
Detection of rise of 9th cycle
Detection of rise of 9th cycle
Figure 14.35 Timing for Setting TRS Bit in Slave Mode
Rev.4.00 Mar. 27, 2008 Page 538 of 882
REJ09B0108-0400