HD64F7144F50V Datasheet, PDF (197/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
2
SW2
1
R/W CS assert period extension for CS2 and CS6 spaces
This bit inserts a cycle to prevent the assert period of RD
and WRx from extending the assert period of CS2 and
CS6.
0: No cycle inserted for CS assert period for CS2 and CS6
spaces.
1: CS assert extension for CS2 and CS6 spaces.
(Each one cycle inserted before and after the bus cycle)
1
SW1
1
R/W CS assert period extension for CS1 and CS5 spaces
This bit inserts a cycle to prevent the assert period of RD
and WRx from extending the assert period of CS1 and
CS5.
0: No cycle inserted for CS assert period for CS1 and CS5
spaces.
1: CS assert extension for CS1 and CS5 spaces.
(Each one cycle inserted before and after the bus cycle)
0
SW0
1
R/W CS assert period extension for CS0 and CS4 spaces
This bit inserts a cycle to prevent the assert period of RD
and WRx from extending the assert period of CS0 and
CS4.
0: No cycle inserted for CS assert period for CS0 and CS4
spaces.
1: CS assert extension for CS0 and CS4 spaces.
(Each one cycle inserted before and after the bus cycle)
Rev.4.00 Mar. 27, 2008 Page 151 of 882
REJ09B0108-0400