HD64F7144F50V Datasheet, PDF (884/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

D. I/O Port Block Diagrams
Function 2
Dn (BSC)
RES
R
Q PDnDR D
C
PDDRL.WR
PDDRL.RD
Dout
AUDMD
Din
Function 2
PFC
Q PDnMD0
Q PDnMD1
Q PDnIOR
SBYCR
Q Hi-Z
Bus release
Software standby
AUD module standby
RES: Reset signal
PDDRL.RD: Port D data register L read signal
PDDRL.WR: Port D data register L write signal
Din: Data input timing signal
Dout: Data output timing signal
Pins
PD14/D14/
AUDCK
PD15/D15/
AUDSYNC
Figure D.26 PDn/Dn/Function 2
Symbol in Figure D.26
Available Products
SH7144
SH7145
PDn Dn
Function
2
Masked ROM
version/
F-ZTAT ROM less
version version
F-ZTAT
version
Masked ROM
version/
ROM less
version
PD14 D14 AUDCK √
⎯
(BSC) (AUD)
⎯
⎯
PD15 D15 AUDSYN √
⎯
(BSC) C (AUD)
⎯
⎯
Rev.4.00 Mar. 27, 2008 Page 838 of 882
REJ09B0108-0400