HD64F7144F50V Datasheet, PDF (564/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. I²C Bus Interface (IIC) Option
14.4.6 Operations in Slave Transmission
When the address of the slave device matches the address which the master device transfers in the
first frame (address receive frame) after start condition detection in slave receive mode, and the
8th bit of data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and slave transmit
mode is entered.
Figure 14.23 is a flowchart that gives as example of operations in slave transmit mode.
Slave transmit mode
Clear the IRIC flag in ICCR
Write transmit data to ICDR
Clear the IRIC flag in ICCR
[1], [2] If the slave address matches the address in the first frame
following the start condition detection and the R/W bit is 1 in slave
receive mode, the mode changes to slave transmit mode.
[3], [5] Set transmit data for the second and subsequent frames.
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Read the ACKB bit in ICSR
No
Transmission
completed?
(ACKB = 1?)
Yes
Clear the IRIC flag in ICCR
Set ACKE to 0 (ICCR)
(Clear ACKB to 0)
Set TRS to 0 (ICCR)
Read ICDR
[3], [4] Wait for 1 byte to be transmitted.
[4] Determine end of transfer.
[6] Clear the IRIC flag.
[7] Clear acknowledge bit data.
[8] Set slave receive mode.
[9] Dummy read (to release the SCL line).
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Clear the IRIC flag in ICCR
End
[10] Wait for stop condition
Figure 14.23 Example: Flowchart of Operations in Slave Transmit Mode
Rev.4.00 Mar. 27, 2008 Page 518 of 882
REJ09B0108-0400