HD64F7144F50V Datasheet, PDF (246/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Direct Memory Access Controller (DMAC)
CK
DREQ
1st sampling
2nd sampling
DRAK
Bus
cycle
DACK
CPU(1)
CPU(2)
CPU(3) DMAC(R) DMAC(W) CPU(4) DMAC(R) DMAC(W) CPU(5) DMAC(R) DMAC(W)
Figure 10.14 Cycle Steal, Dual Address and Level Detection (Fastest Operation)
CK
DREQ
DRAK
Bus
cycle
DACK
1st sampling
CPU
CPU
2nd sampling
CPU
DMAC(R)
DMAC(W)
CPU
DMAC
(R)
Figure 10.15 Cycle Steal, Dual Address and Level Detection (Normal Operation)
Note: With cycle-steal and dual address operation, sampling timing is the same regardless of
whether DREQ detection is by level or by edge.
CK
DREQ
DRAK
Bus
cycle
DACK
CPU
CPU
CPU
DMAC
CPU
DMAC
CPU
DMAC
Figure 10.16 Cycle Steal, Single Address and Level Detection (Fastest Operation)
CK
DREQ
DRAK
Bus
cycle
DACK
CPU
CPU
CPU
DMAC
CPU
DMAC
CPU
Figure 10.17 Cycle Steal, Single Address and Level Detection (Normal Operation)
Rev.4.00 Mar. 27, 2008 Page 200 of 882
REJ09B0108-0400