HD64F7144F50V Datasheet, PDF (176/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. Data Transfer Controller (DTC)
DTSAR
or
DTDAR
First block
•
•
Block area
•
Transfer
Nth block
DTDAR
or
DTSAR
Figure 8.8 Memory Mapping in Block Transfer Mode
Chain Transfer: Setting the CHNE bit to 1 enables a number of data transfers to be performed
consecutively in a single activation source. DTSAR, DTDAR, DTMR, DTCRA, and DTCRB can
be set independently.
Figure 8.9 shows the chain transfer.
When activated, the DTC reads the register information start address stored at the vector address,
and then reads the first register information at that start address. After the data transfer, the CHNE
bit will be tested. When it has been set to 1, DTC reads next register information located in a
consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit
is cleared to 0.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Rev.4.00 Mar. 27, 2008 Page 130 of 882
REJ09B0108-0400