HD64F7144F50V Datasheet, PDF (22/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

17.1.8 Port D Control Registers L1, L2, H1, H2
(PDCRL1, PDCRL2, PDCRH1, PDCRH2)......................................................... 612
17.1.9 Port E I/O Register L (PEIORL).......................................................................... 621
17.1.10 Port E Control Registers L1, L2 (PECRL1, PECRL2) ........................................ 622
17.1.11 High-Current Port Control Register (PPCR)........................................................ 630
17.2 Usage Notes ...................................................................................................................... 631
Section 18 I/O Ports...........................................................................................633
18.1 Port A................................................................................................................................ 634
18.1.1 Register Descriptions ........................................................................................... 636
18.1.2 Port A Data Registers H and L (PADRH and PADRL)....................................... 636
18.2 Port B ................................................................................................................................ 639
18.2.1 Register Descriptions ........................................................................................... 639
18.2.2 Port B Data Register (PBDR) .............................................................................. 640
18.3 Port C ................................................................................................................................ 642
18.3.1 Register Descriptions ........................................................................................... 642
18.3.2 Port C Data Register (PCDR) .............................................................................. 643
18.4 Port D................................................................................................................................ 645
18.4.1 Register Descriptions ........................................................................................... 647
18.4.2 Port D Data Registers H and L (PDDRH and PDDRL)....................................... 647
18.5 Port E ................................................................................................................................ 650
18.5.1 Register Descriptions ........................................................................................... 651
18.5.2 Port E Data Register L (PEDRL)......................................................................... 652
18.6 Port F................................................................................................................................. 654
18.6.1 Register Descriptions ........................................................................................... 654
18.6.2 Port F Data Register (PFDR) ............................................................................... 654
Section 19 Flash Memory (F-ZTAT Version)...................................................657
19.1 Features............................................................................................................................. 657
19.2 Mode Transitions .............................................................................................................. 659
19.3 Block Configuration.......................................................................................................... 663
19.4 Input/Output Pins .............................................................................................................. 664
19.5 Register Descriptions ........................................................................................................ 665
19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 665
19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 666
19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 667
19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 668
19.5.5 RAM Emulation Register (RAMER)................................................................... 668
19.6 On-Board Programming Modes........................................................................................ 670
19.6.1 Boot Mode ........................................................................................................... 671
Rev.4.00 Mar. 27, 2008 Page xx of xliv
REJ09B0108-0400