HD64F7144F50V Datasheet, PDF (175/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. Data Transfer Controller (DTC)
Block Transfer Mode: Performs the transfer of one block for each one activation. Either the
transfer source or transfer destination is designated as the block area.
The block length is specified between 1 and 65536. When the transfer of one block ends, the
initial state of the block size counter and the address register specified as the block area is restored.
The other address register is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt is requested. Table 8.4 lists the register functions in block transfer mode. Figure 8.8
shows a memory map in block transfer mode.
Table 8.4 Block Transfer Mode Register Functions
Register
DTMR
DTCRA
DTCRB
DTSAR
DTDAR
Function
Operation mode
control
Transfer count
Block length
Transfer source
address
Transfer destination
address
Values Written Back upon Transfer Information Write
DTMR
DTCRA – 1
(Not written back)
(DTS = 0) Increment/ decrement/ fixed
(DTS = 1) DTSAR initial value
(DTS = 0) DTDAR initial value
(DTS = 1) Increment/ decrement/ fixed
Rev.4.00 Mar. 27, 2008 Page 129 of 882
REJ09B0108-0400