HD64F7144F50V Datasheet, PDF (505/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Serial Communication Interface (SCI)
13.7.7 Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with the CKE1 and CKE0
bits in SCR. At this time, the minimum clock pulse width can be specified.
Figure 13.29 shows the timing for fixing the clock output level. In this example, the GM bit is set
to 1, the CKE1 bit is cleared to 0, and the CKE0 bit is controlled.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 13.29 Timing for Fixing Clock Output Level
Rev.4.00 Mar. 27, 2008 Page 459 of 882
REJ09B0108-0400