HD64F7144F50V Datasheet, PDF (534/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. I²C Bus Interface (IIC) Option
Bit Bit Name Initial Value R/W Description
2 AAS
0
R/(W)* Slave Address Detection Flag
When the first frame after the start condition matches the SVA6
to SVA0 bits of SAR or when the general-call address (H'00) is
detected in the I²C bus format in the slave receive mode.
[Setting condition]
• Detection of the slave address or general call address (one
frame, including the R/W bit, is H'00) while in the slave-
receive mode and FS = 0.
[Clearing conditions]
• Writing of data to ICDR (during transmission) or reading of
data from ICDR (during reception)
• Writing of 0 to this bit after reading it as 1
• Entering the master mode
1 ADZ
0
R/(W)* General Call Address Detection Flag
In the I²C bus format in the slave-reception mode, the
general-call address (H'00) is detected in the first frame
after the start condition.
[Setting condition]
• Detection of the general call address (one frame,
including R/W bit, is H'00) in the slave-receive mode
(FSX = 0 or FS = 0).
[Clearing conditions]
• Writing of data to ICDR (during transmission) or reading
of data from ICDR (during reception).
• Writing 0 to this bit after reading it as 1
• Entering the master mode
When the general call address is detected while FS = 1 and
FSX = 0, the ADZ flag is set to 1 but the general call
address is not identified (the AAS flag is not set to 1).
Rev.4.00 Mar. 27, 2008 Page 488 of 882
REJ09B0108-0400